I wonder that AD9122's parameter settings in reference design like fcenter, HB1, HB2, HB3, BW?
(4) I think fDATA=491.52MHz(fBus=983.04), right?
The defaults in the reference design use fdata = fdac = 491.52 MHz.
The LVDS interface in in 16-bit Word mode, using a Double Data Rate (DDR) clock.
All HB interpolation filters are in bypass
- thus there is no interpolation (limitation of BW, fcenter shift, etc) and fdata = fdac.
BTW: We’re in progress adding SW driver support for the cascaded Half-Band Interpolation filters with all their mode and options.
I think that AD9122 is set for direct clocking.
According to user manual website->functional overview, fdacclk is provided from AD9523 is 983.04MHz,right?
So, fdac(491.52MHz) is not equal to fdacclk(983.04MHz)?
I could not find the relationship between fdac and fdacclk in AD9122 datasheet.
There are two clocks associated with the DAC.
One is the sampling clock (fdacclk) and one is the Interface/data clock (DCI).
In the reference design we set the AD9523 so that the corresponding outputs supply the same 491.52 MHz clock.
If the wiki told something different, it was a typo.
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