Is there limitation about CLK signal for AD5160?
It could not the right setting by slow slew rate clock signal.
It is OK when SDI is 0xFF or 0x00, but in other setting,it is unstable.
In our test, clock signal spent 10usec to rising or falling.
using buffer, drive more fast, then it is stable.
I don't know it comes from slew rate or other circuit issue.
Could I have a comment ?