I'm using an FPGA and already use an AD699 which works great.
Now I'm trying to drive an AD677 but I have a problem when I want to read the result because I don't have the same (nearly) results each time I want a sample.
Here the part of code to get a sample
mesure : process(Sclk, init, Sdata, Busy)
variable i : integer :=16;
variable data_out_temp : std_logic_vector(15 downto 0);
if (rising_edge(Sclk) and init>=86000) then -- init is only to read after calibration
if i=0 then
If you have some answer ... Thanks