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[Help] ad677 driver for fpga

Question asked by hyrsut on Jan 21, 2013
Latest reply on Mar 12, 2013 by maithil

Hello,

 

I'm using an FPGA and already use an AD699 which works great.

Now I'm trying to drive an AD677 but I have a problem when I want to read the result because I don't have the same (nearly) results each time I want a sample.

 

Here the part of code to get a sample

 

mesure : process(Sclk, init, Sdata, Busy)

variable i : integer :=16;

variable data_out_temp : std_logic_vector(15 downto 0);

begin

 

if (rising_edge(Sclk) and init>=86000) then  -- init is only to read after calibration

 

      i:=i-1;

    Data_out_temp(i):=Sdata ;

   

        if i=0 then

        data_out<=data_out_temp;

         i:=16;

        end if;

 

    end if;

end if;

 

If you have some answer ... Thanks   

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