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Phase synchronization of several ADF4351

Question asked by Alexander on Jan 21, 2013
Latest reply on Jan 23, 2013 by icollins

Hi,

We are working on a project where high data sampling rate (800 MSPS) is necessary. The project is in initial stage now and one of the ideas is to build a time-interleaved ADC system with two 400 MSPS (or four 200 MSPS) ADCs working in parallel and use PLL synthesizers with phase adjust capability. After reading the ADF4351 datasheet i see that it has phase adjust option and several PLLs can be phase synchronized to a common reference. What is the maximum achievable accuracy of phase adjust between outputs of two ICs and are there any constraints that can limit ADF4351 feasibility in such an application?

Alexander

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