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AD9250-FMC-250EBZ

Question asked by aswain571 on Jan 21, 2013
Latest reply on Jan 21, 2013 by rejeesh

Hi, I've downloaded the Xilinx reference design for AD9250-FMC-250EBZ from http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9250-fmc-250ebz

I am attempting to get the design build environment working in my EDK installation (v 14.3). I have done the following:

1) opened the .xmp file with XPS

2) followed the upgrade wizard to bring the project into the 14.3 environment (looks like it was build with 13.1)

3) generated netlists for the pcores using CoreGen

4) attempted to generate netlist for the EDK design using XPS.

 

When I attempt 4) above, I get the following errors:

Inserting wrapper level ...

Completion time: 1.00 seconds

 

Constructing platform-level connectivity ...

Completion time: 0.00 seconds

 

Writing (top-level) BMM ...

 

Writing (top-level and wrappers) HDL ...

 

Generating synthesis project file ...

ERROR:EDK:1405 - File not found in any repository

'axi_jesd204b_rx4_v1_00_a/hdl/verilog/jesd204b_rx4.v'

ERROR:EDK:1405 - File not found in any repository

'axi_ad9129_v1_00_a/hdl/verilog/cf_ddsx_1.v'

ERROR:EDK:1405 - File not found in any repository

'axi_ad9129_v1_00_a/hdl/verilog/cf_ddsx_1.v'

ERROR:EDK:440 - platgen failed with errors!

make: *** [implementation/system_proc_sys_reset_0_wrapper.ngc] Error 2

Done!

 

The files referred to in the errors appear not to exist in my pcores source folders.

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