In ADISIMDDS http://designtools.analog.com/dtDDSWeb/dtDDSMain.aspx when I set AD9834,75MHz ref clock and 1 MHz out clock I get this warning in log:
Caution: The relationship you have chosen between the desired output frequency and Ref Clock * Ref Clock Multiplier may lead to increased spur levels and excessive jitter. This effect is not displayed in the output plots, but can be significant. The desired output frequency should not have an integer or near integer relationship to the internal clock frequency. A near integer relationship causes harmonic spurs to fold back and accumulate in the same spectral region. For best performance, please change either Ref Clock or Desired Output Frequency to eliminate the near integer relationship.
Why? Relationship is 1 MHz / 75 MHz = 0.0133 and not near to 1
In real tests I get a bad sine wave with many spurious frequency (with a 9th order Chebychev LC Low Pass filter with fc=32.5MHz) with sine wave in 1-11 MHz range while in 0-1 MHz and in 12-25 MHz all is fine (higher frequency get attenuated by LC filter with some non-ideal components). Is this behavior related with Warning of ADISIMDDS?