ad7689 16bit sar
cfg : b 0111 0001 1100 01
vref 4.096 V vin : 0 to 3.3 V
*reading analog channel 0
what clock frequency(sck) should i use ?
The internal clock performs the ADC conversion, but you will still need the SPI clock to read the data from the device. Since you are not enabling CFG readback, you’d only need a minimum of 16 SCK falling edges (17 if you’re using busy indicator). Using this in the formula would show that you can use 25MHz for your SCK.
The datasheet shows detailed timing diagrams for RDC mode without a busy indicator (Figure 37) and with a busy indicator (Figure 38).
From your configuration, it seems you are using unipolar input, IN0, referenced to GND, full bandwidth, external reference with temp sensor disabled, sequencer disabled and no read back. Bit 13 is 0, keeping current configuration settings. Please confirm CFG[13:0] bits setting.
With regards to your question, Table 5 on page 8 of the AD7689 datasheet specifies the timing requirements. Your clock period is dependent on what VIO you are using.
Hope this helps.
This did not solve my problem.
my CFG [ 0111 0001 1100 01 ] .
READ DURING CONVERSION -MODE
formula on page 24 says Fsck = (NO. OF sck EDGES / Tdata ).
i am planning to use 25 MHZ for sclk ,since this adc is going to be interfaced with am3359.
is this correct or internal clock will be used during conversion?
if this doesnt help ,could you give me steps or examples for (read during conversion mode)rdc?
Retrieving data ...