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Why my AD1939 doesn't update its samples

Question asked by Vinced on Jan 17, 2013
Latest reply on Jan 21, 2013 by ColemanR

I have a AD1938 in my design with a FPGA and a microcontroller. I use the microcontroller to modify SPI register of the AD1938 and the FPGA to get the audio I2S samples. I've configure the AD1938 to operate at 12kHz in direct clocking mode as a slave; my FPGA is the master. The FPGA gives the ABCLK (768kHz) and the ALRCLK (12KHz) to the AD1938. I monitor the ASDATA1 of the chip and I see the data going to my FPGA, but the word transmitted is never update, it's always the same. I tried the same setting with the AD1938 in Master mode and everything is going alright as expected. I verified my clocks signals and they are exactly the same as in Master mode.


There is my configuration :

Register 0 -> 0x81

Register 1 -> 0x03

Register 2 -> 0x08

Register 3-14 -> 0

Register 15 -> 0x07

Register 16 -> 0x00 (0xC8 when I configure the AD1938 in MAster mode ... for testing)


There is the signals :




Finally, I don't have the right clock in my FPGA so far, I need to order the right one. So the BCLK provide by the FPGA is 762kHz (not 768kHz as expected)