What is the timing spec for the address line setup time to CS on the AD7266?
While the timing spec for the mux ADD pins is not explicitly stated on the datasheet, it does advise that the address lines must be set up prior to the acquisition time and subsequent falling edge of CS\ to correctly set up the mux for that conversion, as is also the case for the SGL/DIFF pin. Please refer to Figure 31 of the AD7266 datasheet, which illustrates this. The maximum acquisition time is specified at 90ns, see Table 1, therefore the ADD pins must be established 90ns or more (e.g. 100ns) prior to the falling edge of CS\.
I moved this question about the AD7266 to the Precision ADCs community. Someone here should be able to assist you.
EngineerZone Support Community Manager
Retrieving data ...