We started by using the reference HDL project available for AD-FMCOMMS1-EBZ board on the Analog Devices web site and successfully implemented it on a Xilinx ML605 development board.
Using the reference HDL project we noticed that changing the DAC sampling rate through software will not change the reference clock frequency that is used by the DAC IP core to transmit data. Could this be a software bug or the DAC sampling rate is fixed in this HDL project?
Furthermore, if we configure the DAC sampling rate to 500MHz and the ADC sampling rate to 166,667 MHz, we noticed that the ADC clock that is sent back to the ADC IP core is slightly below the 166 MHz and the DAC clock that received by the DAC IP core is also below the 500MHz. Moreover, there is also a slight frequency mismatch between the received ADC clock and the DAC clock divided by three. Could this be a problem related to the clock distribution in the AD-FMCOMMS1-EBZ or a software bug that is not configuring correctly the AD9548 or/and the AD9523-1 ICs?