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Interfacing of AD9910 with FPGA

Question asked by waqas on Jan 16, 2013
Latest reply on Jan 17, 2013 by sitti


I am using AD9910, I want to use digital ramp generator. Now my problem is:  when i set jumper 1,2 and 4 to disable and remove jumpers 5,6 and 3.   Then I give reference clock 30MHz and i was expecting 3.75 MHz by default on Sync_clk output but unfortunately i got just noise. In contrast to that when i was using USB cable connected to PC i was getting 3.75 MHz by default on sync_clk.