I've got the standalone reference design working on the ML605. I am now trying to replace the DAC driving logic (DDS) with my own design. Can you tell me what speed the DAC interface works at in the reference design?
Ok, a bit more info:
My DAC data interface runs at 250MHz. To do this I have used the DAC0_CLK_IN_P/N which I believe is 500MHz and divided it by 2 to get the 250MHz so my IQ samples are output at 250MHz. The DCI output (DAC0_CLK_OUT_P/N) runs at effectively half this rate again as it is logic '1' when outputting I samples and logic '0' when outputting Q samples.
With this arrangement do I need to set the dacSamplingRate in main() to 250MHz?
The "dacSamplingRate" controls the frequency of the DACs DACCLK input, which is the clock used by the DAC to sample the input data. In your current setup it's ok to set the "dacSamplingRate" to 250MHz.
Thanks for the response. Am I correct in thinking that if I set this clock to anything but 250MHz I will get problems with the DAC FIFO (overflow or becoming empty)?
Yes, this clock controls the FIFO read rate. If it is different than the data rate than the FIFO will overflow or become empty.
Can you see any problems with the following?:
I have removed the DAC interface from the EDK reference design (axi_dac_4d_2c_0) which in turn removes the DDS etc. I have then hooked up my own design which generates roughly 5MHz tone to the DAC interface. This runs from the DAC0_IN_CLK_P/N (500MHz divided by 2).
In software I've set the dacSamplingRate to 250MHz and removed the SED operation as well as removed the DDS setup (since these modules aren't in the hardware anymore).
From my intial test it looks like the DAC0_IN_CLK_P/N isn't running. Can you think of anything I may have done to cause this in removing those parts of the design? I assumed if the AD9523, AD9548 and AD9122 setup is still being done this clock would be running.
The DAC0_IN_CLK_P/N is generated by the AD9523, so if this part is configured properly then this clock should run regardless of the fact that the DAC interface is present or not in the reference design. The software setup of the AD9523, AD9548 and AD9122 does not use the DAC interface so it shouldn't be affected by the fact that it was removed. Can you probe the DAC0_IN_CLK_P/N clock with a scope to make sure that it is generated on the board and it's not just that by some reason it doesn't get to the new HDL?
I spotted what is hopefully my problem. I have the reference design as a sub-module in a planAhead design with the rest of my logic. When I removed the DAC0 interface from the EDK design I managed to miss bringing the LOC constraints for the DAC0_CLK_IN_P/N pins up in to the planAhead constraints!
Just doing another build now.
Thanks for confirming what I have done so far should be ok. Hopefully I will find out later this morning.
Well i've got something:
But something's not quite right.
If anyone has any clues as to what might be going wrong here i'd appreciate their input.
Can anyone confirm that the reference design DAC interface operates in WORD mode? And if so I assume the FRAME output is not actually used?
I'm a bit stumped as to what i'm doing wrong to end up with the waveform above.
It is word mode. Frame is used to reset the FIFO pointers in MIMO. You are running the DAC at divide by 2 right? Did you setup the OSERDES correctly (if you are using it) or the ODDR?
Ok, so I'm not operating in MIMO so i've got the FRAME_P output set to '0' and FRAME_N set to '1'.
What do you mean 'running the DAC at divide by 2'? The dacSamplingRate is currently set to 250MHz in main() but i've tried setting it to several values with no real noticeable effect (100MHz, 125MHz etc).
The DAC interface from the FPGA runs from the DAC0_IN_CLK_P/N @ 500MHz divided by 2 in an MMCM. I'm running in word mode so I have interleaved I and Q data with the DCI outptu set to '1' when outputting I data and '0' when outputting Q data. So the data interface to the DAC runs at 250MHz.
I don't use the OSERDES as you have done in your design as I found it a little confusing (might be as it's in Verilog and i'm a VHDL guy). My source data is generated at 125MHz so I didn't need to interpolate the extra samples. I have used registers and then instructed MAP to place FF in the IOBs resulting in using the OLOGIC as shown in the screen grab (which shows DAC_DATA(15) for example).
Does that implementation look ok?
What do you have inside the OLOGIC? Can you post a snippet of your output logic? Just the part where you transfer your samples @125MHz to the DAC outputs (including the LVDS buffers).
Inside the OLOGIC there is an FDE. I've attached my DAC IF VHDL file as I can't paste in to this text editor (might be my browser, IE7).
Your question has made me look at the code a bit harder. Of course I have got a clock domain crossing from the 125MHz domain to the 250MHz domain which I may not have dealt with properly. I'll see if I can think of a safer way of doing that. Since it's a bus maybe a dual port FIFO would be the best way.
You will have to change that. Any variations of FDxE will not work (SDR). If you are running the DAC interface at 250MHz, it has to be a DDR element. If I may suggest, you don't really need to use a FIFO (the BRAM clocks are frequency limited than registers -may not run at 500MHz - if you plan to increase the interface clock later), use 4 registers and two 2 bit counters with a signal to synchronize them on both the clocks. If they are coming from MMCM, you can easily generate the synchronous signal from the reset or locked.
Can you explain why it needs to be a DDR interface? If I make it DDR, with a 250MHz clock the data interface is effectively running at 500MHz (new data on rising and falling edge of the 250MHz clock). Are you saying the DAC interface needs to run at 500MHz not 250MHz?
Aren't you generating I and Q? See data sheet word interface mode Figure 43, page 32.
Have a look at the AD9122 datasheet - it requires a DDR interface - check out Figure 46. Timing Diagram for Input Data Port (DCI is the Data Clock Input from the PFGA)
Yes I have the datasheet for the 9122 and am aware of the DDR interface diagrams. Here are some screen grabs of the modelsim simulation of my DAC interface:
The first shows a zoomed in view when you can see the dac_re_data (I) and dac_im_data (Q) being interlaced (dac_data). As my source data is generated at 125MHz I have repeated the data to get the DDR rate (I hope that makes sense).
The second waveform is the simulation zoomed out so you can see the interlaced DAC data shown in analogue form. Here you can clearly see the interleaved I and Q data.
DCI toggles at 250MHz (500MHz DDR). I am now using OSERDES primitives to generate the DAC outputs.
I have also attached the chipscope ADC capture of the resulting waveform which looks better than the previous one but still isn't correct.
Do the modelsim simulation screenshots look correct? (ignoring the fact i've had to repeat the data in order to get the required DDR rate). Perhaps you could upload a similar screengrab of your reference design simulation?
I have just changed the DACCLK channel_divider via the software in AD9523_cfg.h from 2 to 4 and now I have the following waveform in chipscope which looks much more like it.
I'll let Rejeesh comment on the chipscope plots - I'm more interested in why you re-created things from scratch? The designs we put out (I thought) were extensible enough to make a "base" platform where people could build on - the goal was not to have people start over from scratch.
I'm not creating from scratch as such, I've got a design which outputs I and Q data at 125MHz. I wanted to remove the DDS generation from the ADI ref design and replace it with my own. I found the logic driving the OSERSES a bit confusing. Probably partly because it's in verilog and i've only really worked with VHDL. Maybe a document describing the ADC and DAC interfaces in detail would help. (I'm assuming one hasn't been uploaded in the last few weeks that i've missed!).
Also, there's no real description of the clocking structure so I've had to trace through the schematics and then the HDL (MMCM attributes etc) to try to work out what's going on. Hence my original question on this thread of what speed the DAC interface runs at.
Just to say, i totally agree with Adrian, the DAC interface block is very confusing, especialy for those that use VHDL. And for exemple in data OSERDES, the 6:1(or 3:1 I & Q) serialization made by ref design is very not direct to use with our designs (or at least, i dont understand how).
So that we may (if possible) make our designs easy to use- we would like to understand what your design interface is (or what would you like it to be)- 2? How fast you run that interface (250MHz)?
The highest serialization (the lowest internal clock) we can do with a single SERDES is 6 (SDR), hence we used that to run the internal logic at ~166MHz. Not sure why OSERDES is so confusing - if the language really is a problem - you could easily generate VHDL code of the same using coregen and do a comparison. Also one can not miss the fact that the DAC requires a DDR interface.
Well in the future my interface will work around 250MHz, but to start with the reference design my objective is simply send a random signal and then receive it, and after with this same scheme change the sampling clocks and do the same, baby steps . What was confusing me in particular was the serialization 6:1, but from my previous analisys of the design and with your response(166 MHZ SDR), i understand now. My sugestion to improve the understanding of the design is, maybe put a clock tree in the pcores.
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