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Maximum clock of EPPI0?

Question asked by twinboy on Jan 16, 2013
Latest reply on Jan 21, 2013 by JoeT

Hi

 

In the hardware reference, it says the maximum internal frequency of EPPI clock is half of SCLK and the maximum external frequency is 75MHz. But in my project, if the external frequency of EPPI clock greater than 70MHz, the data received from EPPI0 will lost. Is somebody encountered this problem?

 

In my project, the CGU use the exam code of Power_On_Self_Test project setting as CGU_Init(20, 1, 2), and the following code is the configure of EPPI0 and DMA29.

 


// configure EPPI0

*pREG_EPPI0_CTL = 0x0004002C;

*pREG_EPPI0_FRAME = 1920;

*pREG_EPPI0_LINE = 1080;

*pREG_EPPI0_HDLY = 0;

*pREG_EPPI0_HCNT = 1080;

*pREG_EPPI0_VDLY = 0;

*pREG_EPPI0_VCNT = 1920;

 


// configure DMA29(EPPI0 Channel 0)

*pREG_DMA29_ADDRSTART = &RAWSource[0];

*pREG_DMA29_CFG = 0x04A00116;

*pREG_DMA29_XCNT = 1080;

*pREG_DMA29_YCNT = 1920;

*pREG_DMA29_XMOD = 2;

*pREG_DMA29_YMOD = 2;

 

 

Regards,

Junior

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