HI ADI Support,
I am using an audio codec on SPORT1 of BF561 EZ-Kit. The audio codec generates the FSYNC and the Bitclock for the SPORT. The codec generates a 8 kHz FSync and 16 Bit data word per sample but the BitClock is 256 kHz instead of 128 kHz. So the first 16 Bit have the sample data of the audio channel followed by 16 Bit which are not used until the FSYNC occurs. See screenshot in attachment. So actually there are 32 Bits/Clocks between FSYNC but only the first 16 Bits have the audio payload content.
My Sport RCR1 is set to 0x0401
and Sport RCR2 register is set to 0xf which means 16Bit.
Actually between the FSYNC there are 32 Bit. So one option would be to set the RCR2 serial word length to 0x1f. This could be one solution.
I would like to use later the uLaw Compand option which requires 16 Bit data.
My question is now what would be the best settings for Sport RCR1 and Sport RCR2 in order that the second 16Bits are ignored.