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Question asked by rajesh.subramani on Jan 15, 2013
Latest reply on Jan 17, 2013 by danf


1. I am using AD9736 in my design for the waveform generation, it has been interfaced with the XC6VLX195T(Virtex-6) FPGA. The  output of the DAC is 180MHz, DAC CLK=840MHz, mode of operation: 2x mode DATA_CLK=210MHz, IOUT is 20mA, input and output terminations are as per the datasheet recommendation, it seems the output having the spurious of 240MHz which is -39dBc. But the datasheet claims about minimum of 66dBc. How to achieve this level ? What is the source for 240MHz ?

2. How to test the DAC other than using DDS core in the FPGA ?

3. What kind of data is required(including how many samples, how many bits for each sample) to construct the sine waveform of 180MHz using AD9736 & Virtex-6 FPGA with reference clock of 840MHz ?