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The effect of lower sample rate?

Question asked by tinwei0602 on Jan 15, 2013
Latest reply on Jan 15, 2013 by rejeesh

Hi,

     What kind of the effect when we use lower smaple rate?

As I know FPGA's system clock is 200MHz, however clk input from RF board is 491.52MHz.

It is hard to handle/generate waveform, unless we use 3 dds like reference design.

 

BR
Benson

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