What kind of the effect when we use lower smaple rate?
As I know FPGA's system clock is 200MHz, however clk input from RF board is 491.52MHz.
It is hard to handle/generate waveform, unless we use 3 dds like reference design.
In general terms, if your tone is a lower frequency you are okay (but you will be bandwidth limited). You can also try enabling interpolation inside the DAC. The reference design is simply providing the highest interface speed that is possible but keeping the internal clock slowest possible (since a single OSERDES is 3:1 DDR).
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