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Time limit t8(SCLK falling edge to FSYNC rising edge time) of AD9837

Question asked by Kaos on Jan 15, 2013
Latest reply on Jan 30, 2013 by Kaos

Dear Sir/Madam,

 

I have a question for your good AD9837 Programmable Waveform Generator.
As for your time limit t8(SCLK falling edge to FSYNC rising edge time) on your fig-3 Serial Timing Chart AD9837 datasheet ,it shows "10ns min / (t4-5)ns max".


Generally I understand that it cannot guarantee the value "t4-5ns" as general SPI peripheral.

I confirmed by the driver for RL78G13/renesas your microcontroller No-OS driver ,so I found that FSYNC was negated after the time longer than (t4-5)ns.
But AD9837 was working as no problem on this timing longer than (t4-5)ns.

 

So I think your AD9837 function as following:

"The timing for t8 it can accept the input FSYNC is 10nsec min to (t4-5)nsec max. When you negate FSYNC after (t4-5)nsec , AD9837 can accept the command normally."

 

Is this correct ,or not?

 

Thanks ,Kaos

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