We recently acquired an AD-FMCOMMS1-EBZ high-speed analog module for high speed RF to digital and digital to RF data communication.
Although the verilog source code is made available on the reference HDL project, several internal operations made by the DAC IP core (axi_dac_4d_2c) and by the ADC IP core (axi_adc_2c) are not clear. In this sense, I wonder if it is possible to have access to documentation (further than the regmap txt files) describing the programming model of such IP cores.
We also noticed that changing the DAC sampling rate through software will not change the reference clock frequency that is used by the DAC IP core to transmit data. Could this be a software bug or the DAC sampling rate is fixed in this HDL project?
Thank you very much.