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ADV7611 timing question

Question asked by HankZ on Jan 14, 2013
Latest reply on Feb 11, 2013 by GuenterL

In Fig 4 of the data sheet, the T11 and T12 WC parameters are 4.0 and 0.3 ns respectively. With a 6.734 ns clock period @148.5 MHz (60p) this gives a data valid window that begins 0.3 ns after the negative clock edge and ends (6.734 / 2 – 4) = 3.367 = 0.633 ns before the next rising edge which results in a 3.367 – 0.3 – 0.633 = 2.434 ns data valid window or about 1/3 of the clock period. With such a narrow window the data actually becomes valid after a falling clock edge and goes invalid before the next rising clock edge. There’s no clock edge to sample it!


I know this part has a DLL which can delay the clock, but determining the correct delay value would require a calibration data pattern from the ADV7612 that would be sampled by our receiving device as the tap values of the DLL are changed.


My question is if the WC values for T11 and T12 are true for this 148.5 MHz clock speed. If they are true, will you tell me how I can produce a predictable data pattern from the ADV7612 such that our interface logic can sample the pattern while our software varies the DLL taps on the LLC signal?


Thanks in advance for your help,