I am locking my pll to frequency 4800MHz with reference frequency 50MHZ(PFD frequency is the same), and with adf4107 synthezier. I see that pll had locked to frequncy but when i am unlocking pll by unplugging vco signal digital lock detect signal doesnt fall to digital zero level(it falls only to 2 volts or stays the same 2.9 V). When PFD frequency is 25MHZ everything is ok. What is the reason of such behavior?
Initialization latch 0x9f 0x80 0x93
function latch 0x9f 0x80 0x93
R counter 0x10 0x0 0x4
AB counter 0x0 0x3 0x1
I had the similar issue with ku-band pll 6400MHz frequency and reference 50MHz. When reference signal unplugged digital lock detect signal was something like oscillating with frequency 1Hz. And again when PFD frequency was 25MHz everything was ok(reference was 50MHz) .