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Question on PLL (getting better phase noise output)

Question asked by gouzou on Jan 11, 2013
Latest reply on Jan 11, 2013 by pkern

Dear all,

 

Hello and happy new year 2013,

 

I'd like to ask a question based on pll/clock generation.

Based on this FAQ: http://tinyurl.com/ah7r5ju there is a benefit from running a VCO at very high frequency, higher than the Fpdf or Fref. But this leads to a high N value right?

Based on this pdf http://www.analog.com/library/analogDialogue/cd/vol33n1.pdf page 20, right column, it is stated that:


"Integer N synthesizers require a reference frequency that

is equal to the channel spacing. This can be quite low and thus

necessitates a high N. This high N produces a phase noise that

is proportionally high."

 

So, what i'm thinking of wrong?

 

Thank you.

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