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Timer sync problem (BF537)

Question asked by carber on Jan 10, 2013

Hi,

I'm having trouble getting TIMER3 to assert on the rising edge of PPI_CLK when also using PPI.

In the HRM it says: The TMRx pin transitions on rising edges of PWM_CLK. There is no way to select the falling edges of PWM_CLK.

 

PPI_CLK = TMRCLK = DOTCLK

 

I'm using 3 sync signals (FS3 is not used) and everything is clocked with PPI_CLK:

HSYNC -> FS1

VSYNC -> FS2

ENABLE -> TIMER3

 

TIMER3 configuration:

set_gptimer_period(TIMER_ENABLE_id, fbi->h_period);  
set_gptimer_pwidth(TIMER_ENABLE_id, fbi->h_actpix);  
set_gptimer_config(TIMER_ENABLE_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |  
           TIMER_TIN_SEL | TIMER_CLK_SEL |  
           TIMER_EMU_RUN);  

FS1 and FS2 timer configurations:

set_gptimer_period(TIMER_HSYNC_id, fbi->h_period);  
set_gptimer_pwidth(TIMER_HSYNC_id, fbi->h_pulse);  
set_gptimer_config(TIMER_HSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |  
           TIMER_TIN_SEL | TIMER_CLK_SEL |  
           TIMER_EMU_RUN);  

set_gptimer_period(TIMER_VSYNC_id, fbi->v_period);  
set_gptimer_pwidth(TIMER_VSYNC_id, fbi->v_pulse);  
set_gptimer_config(TIMER_VSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |  
           TIMER_TIN_SEL | TIMER_CLK_SEL |  
               TIMER_EMU_RUN);  

 

I have tried 4 PPI configurations, 2 of them have this problem:

 

#1

bfin_write_PPI_DELAY(fbi->h_start);  
bfin_write_PPI_COUNT(fbi->h_actpix - PPI_COUNT_CORR_OFFSET);  
bfin_write_PPI_FRAME(fbi->v_lines);  
bfin_write_PPI_CONTROL(PPI_TX_MODE |  
        PPI_XFER_TYPE_11 |  
        PPI_PORT_CFG_01 |  
        DLEN_16);  

 

rgb.png

 

FS1 and FS2 are asserted on falling edge (should be rising).

Data is driven on falling edge (OK!).

TIMER3 is asserted on rising edge (OK!).


#2

bfin_write_PPI_DELAY(fbi->h_start);  
bfin_write_PPI_COUNT(fbi->h_actpix - PPI_COUNT_CORR_OFFSET);  
bfin_write_PPI_FRAME(fbi->v_lines);  
bfin_write_PPI_CONTROL(PPI_TX_MODE |  
        PPI_XFER_TYPE_11 |  
        PPI_PORT_CFG_01 |  
        DLEN_16 |  
        PPI_POLS_1);  

 

rgb_pols.png

 

FS1 and FS2 are asserted on falling edge (OK!).

Data is driven on falling edge (OK!).

TIMER3 is asserted on rising edge (OK!).


#3

bfin_write_PPI_DELAY(fbi->h_start);  
bfin_write_PPI_COUNT(fbi->h_actpix - PPI_COUNT_CORR_OFFSET);  
bfin_write_PPI_FRAME(fbi->v_lines);  
bfin_write_PPI_CONTROL(PPI_TX_MODE |  
        PPI_XFER_TYPE_11 |  
        PPI_PORT_CFG_01 |  
        DLEN_16 |  
        PPI_POLC_1);  

 

rgb_polc.png

 

FS1 and FS2 are asserted on rising edge (OK!).

Data is driven on rising edge (OK!).

TIMER3 is asserted on falling edge (should be rising).


#4

bfin_write_PPI_DELAY(fbi->h_start);  
bfin_write_PPI_COUNT(fbi->h_actpix - PPI_COUNT_CORR_OFFSET);  
bfin_write_PPI_FRAME(fbi->v_lines);  
bfin_write_PPI_CONTROL(PPI_TX_MODE |  
        PPI_XFER_TYPE_11 |  
        PPI_PORT_CFG_01 |  
        DLEN_16 |  
        PPI_POLC_1 |  
        PPI_POLS_1);  

 

rgb_polc_pols.png

 

FS1 and FS2 are asserted on rising edge (should be falling).

Data is driven on rising edge (OK!).

TIMER3 is asserted on falling edge (should be rising).

 

Here is a block diagram of the HW:

 

ppi.jpg

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