AnsweredAssumed Answered

ADV7513 does not lock PLL

Question asked by marcol on Jan 10, 2013
Latest reply on Jan 15, 2013 by mattp

when I power up via Register 0x41 (setting reg from 0x52 to 0x12)  the adv7513 I see the lower 4 bits getting set, but after a few seconds the register gets stuck at 0x0e of 0x0f.

This happens on 3 boards ( I do not have more), one adv7513 already changed, same result. the power for the PLL has a separate LDO and is pretty clean.

The VIC register shows always the right VIC. I use 27 Mhz Video clock(2x) with 656 embedded sync and 32 khz Audio sample rate. Audio Master is at 12,288 Mhz

I'm wondring why the CTS Automatic field does sty at 0.

What can I do and is there a description for the lower 4 bits of the PLL register?