With a scope set to trigger off of the clock input to the XTALI pin and simultaneously looking at the CLKOUT pin, I observe about 5nSec of jitter over time with between the two clock signals. This is true of a couple of in house designs. The PLL components are as close as possible to the chip. I also see about this same amount of jitter when I look at the ADAU144x evaluation board.
Is this to be expected and if so is there a specification for this?
I note that if I touch the PLL node with a scope the jitter goes away. Are there other recommended PLL values?