Question: How can I force free run so HDMI receiver outputs syncs with flat picture of a chosen color?
The following script should work on all ADV7610, ADV7611, ADV7612 and ADV7619.
You can select video standard (480i, 576i, 480p, 576p, 720p, 1080i, 1080p, 640x480, 800x600, 1024x768, 1280x1024) by selecting properly regiseters 98 00 xx and 98 01 xx. Refer to UG-216 for more details.
Free-run color is chosen via registers 44 C0 xx.. 44 C2 xx
98 FF 80 # I2C reset
98 FD 44 # CP
98 00 1E # VID_STD = 1080P60 @ 60Hz
98 01 05 # Prim_Mode =101b HDMI-COMP
98 03 42 # 36 bit SDR 444 Mode 0
98 05 28 # AV Codes Off
98 0B 44 # Power up part
98 0C 42 # Power up part
98 14 7F # Max Drive Strength
98 15 80 # Disable tristate
98 19 83 # LLC DLL phase
98 33 40 # LLC DLL enable
44 BA 01 # Set HDMI FreeRun
44 BF 17 # FORCE FREE RUN; Manual color settings
44 C0 00 # Manual color: Green channel
44 C1 00 # Manual color: Red channel
44 C2 A0 # Manual color: Blue channel
44 C9 05 # Disable auto buffering of free-run parameters
When I try to change the 0x98, FF (main reset register) = 0x80, I get and I2C error if I am runnig the DVP Evaluation Software. I tried toggling the software switch up and make the register changes but still same I2C problem.
I think what Vito provided above is intended to be run as a script (as opposed to being manually entered into the DVP Evaluation Software).
If you prefer to manually enter this into the DVP Evaluation software, ignore the "I2C reset" statement.
I tried doing that starting with the 1080p script and I got a black screen without noise but not showing anything from my HDMI input. Withouth EDID is there a way that this display would be detected by the cimputer that provides the HDMI?
Please note that the script above only configures the HDMI receiver. If you are trying to get this to work on one of our evaluation boards, you will need to configure the HDMI transmitter also.
If you can't get this to work on your evaluation board, start a new thread and I'll send you a complete script.
98 FF 80 is a self-clearing reset. It causes whole part to reset (including I2C block) and this is the reason why this write is not acknowledged. You should ignore any NACK that occur at the time of performing this write.
Moreover - because 98 FF 80 is self clearing - it will automatically revert to 98 FF 00. (you will not be able to read back 80). There is no need to change this reg.; you may want to add delay after it before performing next writes.
Hope this helps,
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