our development involves an Arm processor using SigmaDSP to output Audio to Headphones/Speakers.
Following is a simplified sequence of operations from ARM's point of view:
starts up (I2S is not yet setup)
Loads SigmaDSP VIA I2C (is programmed as I2S Master)
via I2C, command is sent to SigmaDSP to switch to I2S Slave (main intention is to stop the Master Clock from SigmaDSP)
ARM I2S is programmed as a slave and transmit buffer is loaded
via I2C, command is sent to SigmaDSP to switch to I2S Master to start normal I2S audio transfer
The above either works or is out of sync; almost 50-50 chance.
Note: The ARM I2S stipulation is that it is a Slave and so should be fully loaded and ready before the Master Clock arrives. Thats the reason for this Master/Slave mode switching.
Is there any reason SigmaDSP (I2S) should not be switched from SLAVE to MASTER on the fly?
Any guidance in this matter is greatly appreciated.