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Data corruption in L3 Writeback cached Memory - BF561

Question asked by sunil on Aug 13, 2009
Latest reply on Aug 17, 2009 by Andreas

Hi,

 

            I'm using BF561(Rev 0.5) Ez-KitLite Rev 2.3 with Extender card for audio Talkthrough  application. In the application, CoreA will use VDK and coreB won't use VDK. Extendercard is used for Digital Input/Output support.

 

       To receive input samples, Sport DMA has been enabled. The received data in the Sport Receiver DMA buffer copied to buffer in L3 memory for furthur processing. The receving and copying has been done in core A. L3 buffer is placed in cachable memory. The caching mode used is Writeback.

 

           The problem is data copied to a L3 buffer from DMA buffer is corrupted. Data available in DMA receiver buffer is proper.

 

   We have tested this code by proving sine wave as input.  In our observation we found that successive 3 Left and 3 Right samples are having same values in L3 Buffer. If L3 buffer is not been cached, then data is not getting corrupted. when analysing the addresses of the corresponding data corrupted locations, it is found that from 8th byte of cacheline the data got corrupted/not updated properly.

 

        Please lets us know, If anybody is having any idea why the system is behaving this way.

 

 

-Thara

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