I am using AD7682. The output of AD7682(SDO) is quite strange, which is shown in the diagram.
AD7682 is controlled by a microcontroller. The AD7682 CFG is configured as 0b11110010110001. Read After Conversion mode is selected. The following diagram is the schematic:
The following diagrams are the SDO vs CLK, which are strange:
The first diagram is when the Channel is connected with 3V.
The second is when the Channel is connected with 0V.
It seems that the time for the last bit to discharge is quite long. Is the guess correct?
Or what does the "SLOPE" imply?
Thank you very much.