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AD9467 FMC + Zedboard: Reference design issue

Question asked by sts on Jan 2, 2013
Latest reply on Jan 15, 2013 by sts

Hi,

 

we have a Zedboard here with the AD9467 FMC Eval Board and put the Zedboard reference design on the board:

http://wiki.analog.com/_media/resources/fpga/xilinx/fmc/cf_ad9467_zed_edk_14_1_2012_12_07.tar.gz

 

Running the design we observe two problems:

 

1. Instead of receiving the status messages over the serial interface, we only see useless ASCII characters in the terminal program (program: hterm, set to 57600 baud rate)

However, despite the error in the serial communication link, chipscope can be used to capture the signals from the AD converter.

 

2. In chipscope some samples seem to be wrong (see attachment). In the waveform window of chipscope the following can be observed: Some of the bits in one sample are delayed by one sample, causing the wrong values.

 

The signal generator for the input clock is at 250 MHz and 13 dBm, the test signal is at 10 MHz. No modifications were made to the AD FMC board.

 

Thanks for any suggestions,

Stefan

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