The datasheet for the AD9204 mentions having the option of mulitplexing the output data but does not go into any detail on how to do this. Can someone supply me with the specifics on how to go about doing this?
As David noted, the Interleaved output mode is enabled globally onto both output channels via 0x14, bit 5. Here's a few more tips for using interleaved mode.
Since you typically won't need duplicated interleaved data on both CHA and CHB output ports, the undesired channel output can subsequently be disabled by selecting the desired Channel (A or B) Index at 0x05, bits 1-0, then writing a 1 to local (channel specific) OEB register 0x14, bit 4.
The default order of interleaved (DDR) mode outputs CHA port data as ADC_A/B as shown in d/s fig 3 and outputs CHB port data as ADC_B/A (not shown in d/s), although this can be reconfigured by the customer to either A/B or B/A sequence using the “output Invert” bit 0x14, bit 2.
So in interleave mode (d/s fig 3) the respective A or B data is output for only ½ of the CLK period, latched by both the rising and falling edges as opposed to the non-interleaved mode shown in fig 2.
Please let us know if you have any further questions about the AD9204 ADC family.
This is also referred to as CMOS interleaved mode in the data sheet. The timing is described in figure 3, and you must set bit 5 in serial port address 0x14 to enable this mode. Let us know if you need any additional information. Best Regards,
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