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maximum profile toggle rate .vs. data latency (pipeline delay)

Question asked by Halausteve on Dec 20, 2012
Latest reply on Jan 7, 2013 by Kevin.G

I am a novice looking over the AD9914 datasheet, trying to become an actual user soon.

 

My question that struck me, was that it says the pipeline delay, on page 6 and 7, state delays around 320 SYSCLK cycles, which, if run at 3.5Ghz, is about 100 nanoseconds. I assume that means, say, if I select a previously stored freq/phase/amp profile, with the profile pins, it takes something like 100 nanoseconds for the results to appear at the DDS output.

 

Then, looking on Page 5, it says the Maximum Profile Toggle Rate is 1 SYNC_CLK period,  which if run at max 146 Mhz, works out to about 7 nanoseconds.

 

Does "Maximum Profile Toggle Rate" mean the AD9914 can put out a profile 'chirp'  7 nanoseconds long, then another, with a different profile at 7 nanoseconds long, then another, and another, all different? 

 

 

If there is a 100 nanosecond pipeline where data entering finally leaves, that would imply around 14 profiles making their way thru a pipeline.

 

Am I misinterpreting how the AD9914 operates? or is there really a number of data profiles chosen that are winding their way thru a 100 ns data latency pipeline?

 

Can I interpret, say, profile signals sent by a microcontroller to the AD9914 as like a conductor running an orchestra, where the conductor issues a number of commands, which after a short delay, all come out in sequence?

 

Thanks for anyone who can set me straight.

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