I'm working on a design using the AD9116.
I would like to tie the power pins to:
- AVDD = 3.3v supply
- DVDDIO=CVDD = 2.5v supply
- DVDD = bypass cap only (no external load or supply)
I would then use 2.5v signals (Xilinx V6 LVCMOS25 outputs) for all digital inputs (DB, SPI, CLKIN).
A few questions:
- What's the dropout voltage of the on-board DVDDIO-to-DVDD regulator? The datasheet only mentions the LDO as being used when DVDDIO>1.8v. Hopefully it's less than 700mV (so DVDDIO=2.5v works).
- What are V_ih/V_il for CLKIN when CVDD<3.3v? The datasheet only specifies CLKIN logic levels for CVDD=3.3v, even though CVDD can be as low as 1.8v.
- What are the logic levels for the other digital inputs (DB, SPI) when DVDDIO = 2.5? The closest spec in the datasheet would be interpolating between the levels for DVDDIO=1.8v and 3.3v (doing this implies good compatibility with LVCMOS25; hopefully this is accurate).
Also, a few possible errata in the Rev B datasheet:
- Table 17 says "apply external capacitor"; should probably be "apply external reference"
- The main Features list gives a full scale current range of [4,20]mA. The specs on pg. 5 say [2,20]mA. The Reference Control Amplifier section (pg. 43) implies a minimum of 8mA.
- Footnote 1 (pg 6) seems inconsistent- wouldn't a 10kohm xR_set resistor give a full scale current of 3.2mA (not the 8mA given as typical on pg. 5)? Is this referring to a different resistor?
- Figure 103 suggests a circuit that doesn't comply with the earlier requirement of buffering REFIO for any external use. Maybe it's ok since the typical ADA4899 bias current is 100nA (the stated max output current for the REFIO pin)? Maybe not if the Fig 103 circuit is replicated for both DAC outputs, both using REFIO? Same for the circuit in Figure 104.