We are using the AD7626 in our latest design and would like to support both self-clock and echo-clock just by changing the FPGA load (no hardware jumper to ground on the DCO+ pin). In the design the AD7626 DCO+/- LVDS pins are tied directly to a pair of pins on the FPGA. The FPGA pins can be configured as an LVDS input pair or, by changing the FPGA load, the pin connected to the DCO+ pin can be configured as an output tied to logic '0' in the FPGA. Another twist is I'm using an SRAM-based FPGA that will take several milliseconds to configure during which time the pins tied to the DCO+/- pins are inputs. They would remain inputs (as an LVDS input pair) if I use echo clock mode. If I want to use self-clocking mode the FPGA design loaded would set the DCO+ pin as an output tied to logic '0'. When does the AD7626 "sense" the DCO+ pin connection to decide which mode to use?