AnsweredAssumed Answered

Having issues with SPI clock running in Master mode on ADuC7023

Question asked by mike.mandeville on Dec 18, 2012
Latest reply on Jan 14, 2013 by MMA

We have come across a couple of issues with SPI, one of which is covered by the silicon anomaly er004, however we are also seeing an issue when we set SPIDIV at 0x24 or lower.  

 

We are in master mode, sending 54 bytes of data every 50mS, for SPIDIV of 0x25 to 0x31 we are seeing consistent SCLK periods (for all 54 bytes) with consistent frame time.  At 0x24 the total frame time starts to move around.  At 0x23 and below SCLK starts to run away and is always clocking.

 

FUCLK = 41.78Mhz

Outcomes