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COMIID0 Behaviour (3)

Question asked by ADUzer on Dec 12, 2012
Latest reply on Dec 17, 2012 by PatrickN

I posted this as a follow up question in an answered thread but it doesn't seem to be receiving any attention so thought I'd post it in a new discussion.

 

With transmit buffer empty and receive buffer full interrupt enabled in COMIEN0 (=0x03), if a receiver buffer full interrupt and transmit buffer empty occurred (in any order) then would COMIIDO be 0x04 to indicate the highest priority (2) receive buffer full interrupt, even if the lower priority transmit buffer empty condition occurred first?

 

Assuming this condition, if a single read of COMIID0 was performed to determine the cause of the interrupt followed by a read of COMRX, what would be the resulting value in COMIIDO? Would it be 0x02 indicating priority 3 transmit buffer empty has yet to be serviced or would the read of COMIID0 have also clear the lower priority transmit buffer empty interrupt, leaving COMIID0 = 0x01? Also what would the value of the UART bit in IRQSIG be?

 

What exactly is the issue that has been acknowledged here http://ez.analog.com/message/33210#33210. ?

 

Also, on the same subject:

a) Can you confirm that reading COMIID0 does not affect the condition of COMSTA0, specifically bits TEMP and THRE.

b) Can the changing of ETBEI in COMIEN0 from 0 to 1 affect Bits 2:1 in COMIIDO such that COMIID0 = 0x02, or TEMT or THRE?

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