I am using a TCXO (see attached) as the crystal REF_CLK input for AD9910. A passive crystal is used the evaluation board schematic, but the TCXO is a powered crystal. Do I need to change the suggested connection (a 39pF capacitor at each end of the crystal) to another connection?
The TXCO is a 26 MHz crystal with a 0.8 Vpp clipped sinewave output. Is it necessary to convert it to a square or sine output before feeding in the AD9910? If yes, how can I do it?
For AD9910 with crystal reference clock, should I enable the PLL multiplier (N) and set N = 40 to get a 1.04 GHz internal clock frequency? Also, should the VCO range be set at VCO5 ( 820 - 1150 MHz)?
For the PLL loop filter, what does the loop bandwidth (f_OL) represent? The datasheet gives a formula for the loop filter parameters (p.27) based on the gain of phase detector (K_D) and gain of the VCO (K_V). How will K_D and K_V change the performance of the PLL loop filter?
I found pin 2 (PLL_LOOP_FILTER) and pin 3 (AVDD(1.8V)) to be internally connected, is it normal?