I am using AD9910 evaluation. Before coming to my original problem of chirp generation, as a new user of this evaluation kit I have observed some thing of which I have no explanation. kindly guide me :
- I am providing the external Reference clock to my board, and used PLL multiplier block "without populating loop filter components on Kit" (because I didn't knew at that time) and tried to generate a single tone wave form and I got nothing on output (as it should be because there are no filter component installed) but when I checked the "PFD X Reset" block surprisingly I started to got the output frequencies which are about 1.55 times the desired frequency which I had specified in the GUI (for e.g. 10 MHz appears to be 15.55 and 70 MHz appeared as 108.5 MHz etc..).
- After reading through different experts comment, for using PLL multiplier there has to be a loop filter..so without connecting loop filter, this type of output is just a coincidence or a functionality of which I have no information?
2. I tried to generate chirp signal using only external reference clock (NO PLL multiplier, clk divider disabled) via DRG and OSK mode with these specification
Ref clk= 80 MHz
sweep 0= 0.001 MHz sweep 1= 5 MHz
Rising step size= 0.01 MHz Rising step size= 0.01 MHz
Rising step Interval= 0.003 us Rising step Interval= 0.003 us
I specified the lower and upper frequencies for sweep and the rising step size,but I am not able to specify the rising step interval of my own choice. Software is putting some limit. Instead of 0.003us software itself changes it to 0.05 us. Is there any lower limit of rising step interval?
Thanks in advance