I've gone through the datasheet a couple times, but i still can't make much sense, concerning the following issue:
Say, i'm using a 24.576MHz crystal for the DSP clock, and using 96KHz as an internal sampling rate.
If i have a stereo signal coming in through Sdata0 which is sampled at 44.1KHz, and that's routed through an ASRC, all should be fine and dandy, right?
Or, as a more general question, can the clocks for the serial inputs be somehow "slaved" to the serial data source? Or can / do the ASRC's automatically detect the sampling rate of the incoming data stream and auto-adjust accordingly, in order to output the data at the selected core Fs?
Or, approaching this from a different angle, are the input clocks "pre-determined" in the self-boot data written into the EEPROM, or can they be altered during normal operation of the DSP?