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ADV7341/7401 questions

Question asked by francky Employee on Dec 10, 2012
Latest reply on Jun 11, 2013 by DerekBurke

My customer has a main board with the ADV7401 as input, a StratixII FPGA for algorithm processing, and they will design a companion board which shall use the ADV7341.

The video standard that they have at the input and want to send at the output of this system is PAL square pixel, in 768x576 pixels. (this was RGB on the first run, this is why they redesign to support this mode based on PAL)

This mode is supported with a clock input of 29.5 MHz on the ADV7341.

 

On their main board, they have a crystal at 28.636 MHz, which is used for clocking the ADV7401.

Their desired situation is to use the internal PLL of the ADV7401 to generate the 29.5 MHz clock, so as to clock data out at this frequency.

This pixel clock would then be sent to the companion board for clocking the ADV7341.

Here are the questions :

  1. 1.      Can the ADV7401 support the PAL square pixel mode with 768x576 ? can it clock its output data at 29.5 MHz with good video quality ?
  2. 2.      Which PLL_DIV_RATIO should they use in the ADV7401 PLL to generate an accurate 29.5 MHz clock ?
  3. 3.      What tolerance does the ADV7341 accept on the 29.5 MHz input clock used for the PAL mode ?
  4. 4.      Can ADI provide a typical initialization script file on the ADV7341 for this PAL mode ?

 

Thank you.

-Franck, FAE@ADI

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