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Timer sync problem (BF537)

Question asked by carber on Dec 9, 2012
Latest reply on Jan 10, 2013 by carber

Hi,

 

Im using the PPI with 2 frame syncs (FS1 -> HSYNC, FS2 -> VSYNC),

and TIMER3 as an ENABLE signal.

 

HSYNC and VSYNC are started together and ENABLE is started ~1 PPI_CLK after them.

 

bfin_write_TIMER_ENABLE(TIMER_VSYNCbit | TIMER_HSYNCbit);
SSYNC();
while (bfin_read_VSYNC_COUNTER() < 1)
    continue;
bfin_write_TIMER_ENABLE(TIMER_ENABLEbit);
SSYNC();

 

The problem is that ENABLE gets triggered on the falling edge of PPI_CLK while HSYNC and VSYNC are triggerd in the rising edge.

See attached picture.

This should not be possible according to the datasheet.

"The TMRx pin transitions on rising edges of PWM_CLK. There is no way to select the falling edges of PWM_CLK."

 

The timer settings for all three timers are identical:

set_gptimer_config(TIMER_..._id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |
                                                              TIMER_TIN_SEL | TIMER_CLK_SEL |
                                                              TIMER_EMU_RUN);

 

ppi.png

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