Aduc7020 spi in slave mode, CS pin p1.7 grounded. Then, after reset, no data available on MISO. If CS not grounded during reset, but grouded manualy after reset - all is ok. Can I ground CS pin?
Unfortunately the only way to reset the SPI shift counter/register on a ADuC7xxx is a RESET - maybe a SW-RESET.
AS this requires too much time and normally isn't appreciated I have implemented for test a workaround with the PLA.
This is basically a 3-Bit counter and in each SPI interrupt or after a time-out if not enough SPI clocks have been arrived at the slave, software is checking that the counter is 0. If not it clocks the SPICLK gated through the PLA by software till the 3-Bit counter is 0 again. This worked perfect and fast, but requires some extra PIN's and software, but not all - some pin's in the example are only used to bring internal states out for the scope - some doc and software attached. The example is implemented for ADuC7023, but should work for any ADuc7x2x...
In slave mode it is not recommended not to use /CS - or to simply ground it. Anyway, I would recommend to use the SPI on the ADuC7023 as a master if somehow possible.
We have already decided of using Aduc7021.
"not recommended not to use /CS - or to simply ground it" Not clear...
Our device is constantly accepting data from master. So there is no chip select line at all. What can you recommend in this circumstances?
If you do not use the /CS signal you have no control about start and stop of a frame.
You may use a GPIO from the ADuC7021 itself to toggle the /CS, but still there is a potential problem if you have noise on the SPICLK. This can cause a extra bit shift on the SPI and without a more complex workaround using the PLA, the only solution is to do a SW-RESET of the whole part to resolve this. So the other direction - use ADuC7021 as Master is more solid.
"This can cause a extra bit shift on the SPI and without a more complex workaround using the PLA,"
This is potentially very dangerous problem... which I failed to take into account...
What workaround do you mention?
Is there any ability to flush shift register of SPI?
But let me ask you further.
I can unhide a bit the structure of our system:
It has a number N of SPI slave intermediate units, spi master unit, which terminates a chain and Accumulation unit (also SPI slave, but another mcu onboard).
The Accumulation unit triggers data upload from aduc units by synchronization pulse. When this pulse reaches terminal unit it starts clocking as an SPI master and shifts to the line MOSI 2*8*N bits. First 2*8 bits is self ADC result of terminal unit.
Each intermediate units works as an retransmitters. But it shifts 2 bytes of its own adc result on the first 2*8 clocks. Other bits are transmitted "as is".
So, the Accumulation slave unit receives a pocket of 2*8*N bits of data that contain N*16 bits ADC results corresponding to the trigger pulse time.
SPI clock speed is about 4 MBps. MCU are near their reaction limit.
And we have grounded SS\ pins...
I can allow transmitting errors in one trigger cycle, but I want to reset the SPI states/counters at the beginning of a new trigger cycle. And your suggested solution do this.
Does the rising edge of SS\ pin reset internal SPI state/counter?
What toolchain do you use for simulation/debugging bits and pins of ADuC?
I use normally no simulation only real HW and scope to see what happens - as tools for development we either use Keil MDK or IAR Embedded Workbench - but plan to start to get some experience with GCC, eclipse & GDB on ADuCs
For the configuration of the PLA we use the PLATOOL, we provide with our evaluation CDs for ADuC7x2x.
After having thought a moment about your application, I think it may be easier to simply use the PLA.
With the 3-Bit counter, as in my example, simply shift through the bits to 8 PLA elements and use the counter for a interrupt every 8-bits. This removes the requirement to transfer the data from SPIRX to SPITX on the ADuCs and you can easy implement some SW to reset the whole PLA logic in case of error. Also think about how you will check the data you transfer that it is valid - one idea could be to use the highest 4 bits (12 bit ADC data + 4 bit for some coding) ... !?
Thanks, good idea about 4bit CRC.
You do not answer about
"Does the rising edge of SS\ pin reset internal SPI state/counter?"
No - that's the problem why I did this PLA solution.
What would be if:
1. Switch off and on by SPICON.0 ?
2. Change from slave to master and back by SPICON.1 (this would reset shift register imho, or there is another one shift register for master mode?) ?
Wher the internal block structure of SPI module could be found?
As the SPI is normally simple, we did not provide a block diagram so far.
But here below a quick drawing:
Retrieving data ...