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ADSP-21369 SDRAM failed to load.

Question asked by ymwlike on Dec 7, 2012
Latest reply on Jan 3, 2013 by Harshit.Gaharwar

Target Chip:ADSP-21369KSWZ-1A 208pin
SDRAM:MT48LC4M32B2

write to SDRAM but read all FFFF,

So I do not know my SDRAM initialization incorrect Or hardware settings.

Here is my initialization and hardware settings:

#include <def21369.h>
#include <cdef21369.h>

void InitPLL_SDRAM(){

/********************************************************************************************/

int i, pmctlsetting;

//Change this value to optimize the performance for quazi-sequential accesses (step > 1)
#define SDMODIFY 1

    pmctlsetting= *pPMCTL;
    pmctlsetting &= ~(0xFF); //Clear

    // CLKIN= 24.576 MHz, Multiplier= 21, Divisor= 2, CCLK_SDCLK_RATIO 2.
    // Core clock = (24.576 MHz * 21) /2 = 258 MHz  
    pmctlsetting= SDCKR2|PLLM21|PLLD2|DIVEN;
    *pPMCTL= pmctlsetting;
    pmctlsetting|= PLLBP;
    *pPMCTL= pmctlsetting;

    //Wait for around 4096 cycles for the pll to lock.
    for (i=0; i<6096; i++)
          asm("nop;");

    *pPMCTL ^= PLLBP;       //Clear Bypass Mode
    *pPMCTL |= (CLKOUTEN);  //and start clkout
    // Programming SDRAM control registers and enabling SDRAM read optimization
    // CCLK_SDCLK_RATIO= 2.5
    // RDIV = ((f SDCLK X t REF )/NRA) - (tRAS + tRP )
    // (129*(10^6)*64*(10^-3)/4096) - (7+3) = 2015   0x7DF

    *pSDRRC= (0x7DF)|(SDMODIFY<<17)|SDROPT;

    //===================================================================
    //
    // Configure SDRAM Control Register (SDCTL) for PART MT48LC4M32B2
    //
    //  SDCL3  : SDRAM CAS Latency= 3 cycles
    //  DSDCLK1: Disable SDRAM Clock 1
    //  SDPSS  : Start SDRAM Power up Sequence
    //  SDCAW8 : SDRAM Bank Column Address Width= 8 bits
    //  SDRAW12: SDRAM Row Address Width= 12 bits
    //  SDTRAS7: SDRAM tRAS Specification. Active Command delay = 7 cycles
    //  SDTRP3 : SDRAM tRP Specification. Precharge delay = 3 cycles.
    //  SDTWR2 : SDRAM tWR Specification. tWR = 2 cycles.
    //  SDTRCD3: SDRAM tRCD Specification. tRCD = 3 cycles.
    //
    //--------------------------------------------------------------------

    *pSDCTL= SDCL3|DSDCLK1|SDPSS|SDCAW8|SDRAW12|SDTRAS7|SDTRP3|SDTWR2|SDTRCD3;

    // Note that MS2 & MS3 pin multiplexed with flag2 & flag3.
    // MSEN bit must be enabled to access SDRAM, but LED7 cannot be driven with sdram
    *pSYSCTL |=MSEN;

    // Mapping Bank 2 to SDRAM
    // Make sure that jumper is set appropriately so that MS2 is connected to
    // chip select of 16-bit SDRAM device
    *pEPCTL |=B2SD;
    *pEPCTL &= ~(B0SD|B1SD|B3SD);

}


Please tell me what the problem? thank you!!!

 

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