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AD9523 PLL 2 VCO Calibration Problem

Question asked by Andrew.Thompson on Dec 6, 2012
Latest reply on Feb 14, 2013 by Andrew.Thompson

Hi,

 

I'm currently having some trouble with getting an AD9523 up and running in a new prototype system design I'm working on, where the 2nd stage PLL does not seem to be able to lock. Currently my best guess is that this has something to do with the calibration for PLL 2's VCO but I've included details below for how I've been getting on.

 

So far I have been able to program this chip with what I believe to be the desired register settings (see attahced spreadsheet) for it to operate in the manner we require; running from either a 10MHz input on REF_A (configured for a differential signal) or a 100MHz input on REF_B (configured for a differential signal) with a 100MHz VCXO (configured for a single ended signal on the negative input) connected to the 1st stage PLL and all outputs configured to deliver a 100MHZ LVDS output.

 

To configure the chip I have been using the I2C output from an AD9523 evaluation board (target device address set to 0x60, evaluation device set to address 0x62) with the AD9523Eval software. The majority of the device registers have been configured using the GUI before using the I2C debug terminal to program the EEPROM buffer segment, ensure that the VCO calibration bit is set and then to initialise the EEPROM write.

 

After carrying out the above configuration routine  I believe that the chip should be capable of loading its registers from the EEPROM and running a calibration at power on (the EEPROM_SEL line is pulled high on our design to enable this). However on start-up the IC reports that although the 1st stage PLL is locked and running correctly PLL 2 has not locked and so there are no clocks present on the output of the device.

 

When the device is in this partially running state I am able to set bit 4 in register 0x00F3 to force the release of the distribution synch while PLL2 is unlocked to enable the clock outputs; however the resulting output clocks  run at approximately 113.5MHz which would indicate that PLL2 is running far above its upper limit of 4GHz (currently PLL 2 should be locking at 4GHz to enable the 100MHz outputs). Carrying out a manual calibration at this point (either using the Cal VCO button in the Eval software or manually programming the device registers as outlined on page 23 of the data sheet), or before the force release of PLL 2, does not appear to make any difference to the operating frequency of the output clocks.

 

I have also notice during debugging that the AD9523Eval software regularly checks the contents of register 0x0003 which is not listed in the data sheet. I was therefore wondering if it is possible that there are some missing registers that need to be programmed to get the IC configured correctly.

 

If someone would be able to suggest any possible routes forward at this point,  it would be much appreciated as this problem is currently holding up the remainder of the debug and commissioning work that we need to do on our prototype system.

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