I'm a newcomer here. I am using ADIsimPLL 3.43 and I'm planning to design a loop filter for ADF4002 but I don't know how to design the loop filter. I have an external VCXO (Vectron VV-800) which operates at 50 MHz. I used an external 10 MHz from signal generator to fed in ADF4002 evaluation board . My desired loop bandwidth is at 10kHz and phase margin at 45 deg. After the first simulation I implemented the resistor and capacitor values of the loop filter to the ADF4002 evaluation board but in the R&S FSUP Phase Noise Analyzer, it measures and detect correct frequency 50 MHz, however the phase noise in the actual run from the phase noise analyzer is too different from the simulated phase noise. Please help me in the loop filter design.