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AD9548 - Sync on Phase Lock

Question asked by Fred1 on Dec 5, 2012
Latest reply on Dec 6, 2012 by pkern



I am having trouble with the self disciplining feature of the AD9548 PLL.


- I am using 2 EV-Boards with identical settings and output divider settings.

- Both boards are set in self disciplining mode on phase lock.

- The input reference is phase master

- The PLL output frequency is set to 230MHz which goes in the divider network to produce e.g. 10MHz on OUT1.


There is now the following issue:


- After the PLL is phase locked and synchronized the output divider, the 10 MHz signals of both boards should be phase aligned.

- In reality they can be +/-4.3ns ( one 230MHz period) misaligned which is not acceptable for my application.


Is there a way to improve the synchronization between the 2 boards so they will synchronize at the same 230MHz zero crossing?

The 230MHz frequency is phase aligned on both boards so this is not the problem...