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SPI slave core transmit problem

Question asked by SebastianD on Aug 3, 2009
Latest reply on Sep 17, 2009 by robertmce

Hi,

 

I'm trying to set up a SPI link between two Blackfin processors.

 

The master Blackfin is using DMA for receive and transmit, the slave device will use core mode (TIMOD 01 and 00).

 

The hardware link between both devices is working, the slave is receiving and transmitting data from/to the master.

 

But the received and transmitted data is corrupt. It looks like data is shifted by one bit or the last bit is missing. Looking on the signals by an oscilloscope shows that the ISR routine is called at the very beginning of the last bit, before it is sampled (in SPI mode 1 and 3). In SPI mode 0, ISR triggering is OK but data transmit by slave starts one bit later than expected thus the last bit is not transmitted correctly.

 

on the master SPI_CTL = 0x1c06

on the slave SPI_CTL = 0x4c24

Slave select is handled by software.

 

Any help on this problem is appreciated.

 

Best regards

 

Sebastian

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