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One clock signal on your evaluation board AD9239

Question asked by Kaos on Dec 3, 2012
Latest reply on Dec 3, 2012 by Kaos

Dear Sir/Madam,

 

I am just confirming your schematic of AD9239 evaluation board as following.

http://www.analog.com/static/imported-files/eval_boards/AD9239_schematic.pdf

On your schematic, CLK signal seems to send other FPGA on sheet 3 of 5.

 

Question

If I will communicate AD9239 to FPGA, should CLK signal of AD9239 connect to FPGA?

Otherwise should FPGA have another clock signal on external FPGA part(eg; PLL on FPGA) as the recovery-clock?

I am not clear which is better design 1 same clock or 2 clocks.....

Does 1 same clock mean the synchronizeation between FPGA and AD9239??

Why did you design by only 1 clock?

Please give me your good comment.

 

Thanks, Kaos

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