I am just confirming your schematic of AD9239 evaluation board as following.
On your schematic, CLK signal seems to send other FPGA on sheet 3 of 5.
If I will communicate AD9239 to FPGA, should CLK signal of AD9239 connect to FPGA?
Otherwise should FPGA have another clock signal on external FPGA part(eg; PLL on FPGA) as the recovery-clock?
I am not clear which is better design 1 same clock or 2 clocks.....
Does 1 same clock mean the synchronizeation between FPGA and AD9239??
Why did you design by only 1 clock?
Please give me your good comment.