I have a AD9467FMC-250EBZ evaluation board. I would like to know if there is Zedboard support for this board. I'm assuming there is, since ADI provides an advertisement for it in the box.
I have uploaded the working zed design. As you have experienced already, there were timing issues with axi interconnect and dma. I lowered the frequency of DMA to 100MHz@64, ADC is 250MHz@16. The reason I use 200MHz for DMA is because the same setup is used for other projects.
It should be easy to port, but I don't think we have one at present.
I have had a hard time porting this design to the Zynq board that I am using. I first tried on the Zynq ZC702 which is the artix fabric Zynq. I was not able to pass timing, which is not a surprise since it is the slower grade fabric. I had much more success with the port to the Zynq ZC706 which is the Kintex fabric family. The fabric resources in the the ZC706 are similar if not identical to the KC705. In the port to the ZC706 I was atleast able to see ADC samples in chipscope. The problem is that the delay units are not working correcly. I get the error "adc_setup: can not set a zero error delay!". I am assuming that the eye pattern delay calibration is not working correctly. I have tried several different ways to clock this design. In Zynq the Processing System has its own clocks that can be used to drive fabric engines. I have tried having the Processing System generate the delay_clk for axi_adc_1c, that didn't work. I then brought in the external 200MHz reference clock into a clock generator to generate the clocks I needed just like the reference design but I still get the same error. I have noticed when I put the ADC into a test mode (i.e. Mid-Scale Short) that the value (0x1000) jumps back and forth between D15:D1 and D14:D0. Is that right? And sometimes that value on the most significant nibble is 1100. So both D15 and D14 are showing 1 which should not be the case in the MS Short test mode. I thought this was going to be an easy port but it has not been. Any suggestions?
Is the routine fails because the IDELAYCTRL can not lock? If so, q quick solution would be to manually adjust the delay.
I am going to port the design on the Zed board (same device as ZC702).
I will update the wiki page with the result.
Could you please post the link to the uploaded files here in EZone so people can be redirected to that site?
We now have different file names depending on ISE version and date. So a link based on file name may become obsolete. At this time, the following links should work:
It is always safe to go to the wiki page and download it from there.
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