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PLL's for Low Jitter Clock applications

Question asked by ChrisH Employee on Jul 31, 2009
Latest reply on Jan 27, 2011 by Vishnu

In the ADF4001 (rev A) datasheet, on Page 13, there is an application for a "low jitter" clock source for GSM applications.

We have feedback that this circuit can achieve about 2ps jitter with a VCXO and the PLL loop bandwidth limited to about 10Hz. (also simulates pretty well in ADIsimPLL).

 

Are there better, lower jitter implimentations?

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