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Can AD7328's Chip Select be kept low for multiple conversions?

Question asked by shall123 on Nov 27, 2012
Latest reply on Dec 3, 2012 by KarenNE

page 28 of the AD7328's datasheet states the following:

"To complete the conversion and access the conversion result 16 serial clock cycles are required. At the end of the conversion, CS can idle either High or low until the next conversion."

 

Does this mean the chip select can be kept low during multiple conversions? 

 

If not, does Analog Devices have an ADC that allows the chip select to stay low during multiple conversions?

 

Stephen

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